This patent relates to capacitive transducers, and more particularly to techniques for reducing or eliminating nonlinearities due to feed-through capacitances, and automatic calibration procedures to improve the linearity of capacitive bridges and accelerometers by cancelling parasitic feed-through capacitances.
Transducers convert a general physical quantity (for example, acceleration, pressure, etc.) to quantities that can be processed by electronic circuits. In particular, capacitive transducers produce a change of capacitance, corresponding to the magnitude of the measured input signal. Readout circuits for capacitive transducers transform the capacitance change produced by the transducer to an electrical signal. In the process, the circuits apply voltage waveforms to the transducer electrodes.
A capacitive accelerometer, a capacitive transducer for measuring acceleration, can be designed such that displacement of a set of capacitive plates is proportional to acceleration. Then acceleration can be measured using electronics by measuring the difference in the set of capacitors. A capacitive accelerometer can include a mechanical sensing element and a readout circuit. FIG. 1 illustrates an exemplary embodiment of a mechanical sensing element 100 for a capacitive accelerometer. In this embodiment, the mechanical sensing element 100 includes a proof mass 102 suspended between a first spring 104 and a second spring 106, a first electrode 110 and a second electrode 112. A proximal end of the mass 102 is coupled to the first spring 104 and a distal end of the mass 102 is coupled to the second spring 106. The first spring 104 has two ends; a first end coupled to the proximal end of the mass 102 and a second end coupled to a substrate. The second spring 106 has two ends; a first end coupled to the distal end of the mass 102 and a second end coupled to the substrate. A common electrode M is coupled to the mass 102 and moves with the mass 102 relative to the substrate. The first and second electrodes 110, 112 are stationary relative to the substrate. In this embodiment a positive reference voltage VS is applied to the first electrode 110 and the negative reference voltage −VS is applied to the second electrode 112. A first variable capacitor C1 is formed between the first electrode 110 and the common electrode M, and a second variable capacitor C2 is formed between the second electrode 112 and the common electrode M.
In this embodiment, when the system is at rest, there is a substantially equal nominal gap g0 between the first electrode 110 and the common electrode M and between the second electrode 112 and the common electrode M, creating substantially equal capacitances in the first variable capacitor C1 and the second variable capacitor C2. An input acceleration moves the mass 102 relative to the substrate which varies the gaps between the electrodes and varies the capacitance of the variable capacitors C1, C2. Acceleration in the direction of arrow 120 deflects the mass 102 a distance Δx that is proportional to the input acceleration. This movement of the mass 102 increases the distance between the first electrode 110 and the common electrode M to g0+Δx, and decreases the distance between the second electrode 112 and the common electrode M to g0−Δx, which changes the capacitance of capacitors C1 and C2. The capacitance C of variable capacitors C1 and C2 can be determined by:
                              C                      1            /            2                          =                                            ɛ              0                        ⁢            A                                              g              0                        ±                          Δ              ⁢                                                          ⁢              x                                                          (        1        )            where ∈0 is dielectric permittivity, A is the area of the capacitive plates (which extend into the paper), g0 is the nominal gap and Δx is the displacement due to the acceleration. The readout circuit determines the value of Δx based on the capacitance change in capacitors C1 and C2.
Accelerometers are often implemented in harsh vibration-ridden environments, for example automotive or industrial environments. In these environments, it is desirable to have accelerometers with good linearity, low drift performance and large full scale range. Self-balanced accelerometers are usually chosen for these applications. In self-balanced accelerometers, the capacitance C is proportional to 1/d, where d is the distance between the capacitive plates; and the measured output voltage V0 is proportional to (C1−C2)/(C1+C2). Combining these two relationships provides:
                                          V            o                    ∝                                                    C                1                            -                              C                2                                                                    C                1                            +                              C                2                                                    =                                                            1                                  d                  ⁢                                                                          ⁢                  1                                            -                              1                                  d                  ⁢                                                                          ⁢                  2                                                                                    1                                  d                  ⁢                                                                          ⁢                  1                                            +                              1                                  d                  ⁢                                                                          ⁢                  2                                                              =                                                                      d                  ⁢                                                                          ⁢                  2                                -                                  d                  ⁢                                                                          ⁢                  1                                                                              d                  ⁢                                                                          ⁢                  2                                +                                  d                  ⁢                                                                          ⁢                  1                                                      =                          x                              d                ⁢                                                                  ⁢                0                                                                        (        2        )            where x is the displacement value, d0 is the zero displacement value, d1=d0−x is the distance between the plates of capacitor C1, and d2=d0+x is the distance between the plates of capacitor C2. Equation (2) shows that in the ideal case the output voltage V0 of the self-balanced accelerometer is a linear function of the displacement x. Unfortunately, in actual implementations, there are sources of non-linearity not taken into account in Eq. (2).
Though there are several ways to build self-balanced accelerometers to obtain a reading that is proportional to the displacement of the proof mass, to achieve a highly linear accelerometer it is desirable to have a topology that results in zero residual force upon the application of sensor excitation voltages. There are two main sources of non-linearity in self-balanced accelerometers: feed-through capacitance, and mismatch between the two sensor cores. The dominant source is feed-through capacitance, and it is present in both single ended (using only one core) and differential (using two cores) topologies.
Feed-through capacitance (Cft) is any fixed capacitance between the proof mass and the sense electrodes. The feed-through capacitances Cft arise due to parasitics in the sensor element and due to capacitance between the bond wires. FIG. 2 illustrates the feed-through capacitance in a capacitive core 200, an example of which is shown in FIG. 1. The capacitive core 200 includes a first capacitor C1 between a first sense electrode 202 and a proof mass 204, and a second capacitor C2 between a second sense electrode 206 and the proof mass 204. The capacitive core 200 also includes unwanted feed-through capacitances Cft between the proof mass 204 and each of the sense electrodes 202, 206. Re-deriving Eq. (2) taking into account the feed-through capacitances Cft provides:
                                          V            o                    ∝                                                    C                1                            -                              C                2                                                                    C                1                            +                              C                2                            +                              2                ⁢                                                                  ⁢                                  C                  ft                                                                    =                                                            1                                  d                  ⁢                                                                          ⁢                  1                                            -                              1                                  d                  ⁢                                                                          ⁢                  2                                                                                    1                                  d                  ⁢                                                                          ⁢                  1                                            +                              1                                  d                  ⁢                                                                          ⁢                  2                                            +                                                2                  ⁢                                                                          ⁢                                      C                    ft                                                  A                                              =                                                                      d                  ⁢                                                                          ⁢                  2                                -                                  d                  ⁢                                                                          ⁢                  1                                                                              d                  ⁢                                                                          ⁢                  2                                +                                  d                  ⁢                                                                          ⁢                  1                                +                                                                            2                      ⁢                                                                                          ⁢                                              C                        ft                                                                                    C                      ⁢                                                                                          ⁢                      0                                                        ⁢                                                            d                      ⁢                                                                                          ⁢                      2                      *                      d                      ⁢                                                                                          ⁢                      1                                                              d                      ⁢                                                                                          ⁢                      0                                                                                            =                          x                                                d                  ⁢                                                                          ⁢                  0                                +                                                                            C                      ft                                                              C                      ⁢                                                                                          ⁢                      0                                                        ⁢                                                            (                                                                        d                          ⁢                                                                                                          ⁢                                                      0                            2                                                                          -                                                  x                          2                                                                    )                                                              d                      ⁢                                                                                          ⁢                      0                                                                                                                              (        3        )            which introduces a non-linear term x2 due to the feed-through capacitance.
Nonlinearity due to mismatch in sensor cores occurs in fully differential accelerometers which use two sensor cores. A differential topology can provide better robustness to electromagnetic signals and other stray disturbances. The sensor cores are often two separate elements with the proof masses not connected mechanically. This is often done to save cost since mechanical connection of the proof masses of the two cores with electrical isolation can be expensive in terms of processing. Under this condition the offsets of the sensor cores can be in opposite directions which causes non-linearity because of remnant electrostatic forces as well as the fact that capacitance is inversely proportional to displacement.
A comparison of the magnitudes of the non-linearities due to feed-through capacitance and core mismatch shows that feed-through capacitance is the dominant source of non-linearity. The non-linearity due to a core mismatch of 5 pF (+/−5% core mismatch) is 0.016%. However, the non-linearity due to 50 fF (100 times smaller than 5 pF) remnant feed-through capacitance is 0.43%, which is almost 30 times greater than the core mismatch non-linearity. Even a 10 fF remnant feed-through capacitance causes a non-linearity of 0.087%.
It would be desirable to reduce or eliminate the nonlinearity due to feed-through capacitances. It would also be desirable to have an automatic calibration procedure to improve the linearity of capacitive bridges and accelerometers by cancelling the parasitic feed-through capacitances.